CXMT says fifth-generation DRAM is in mass production, with 50% more gross dies per wafer
On Sunday, September 20, ChangXin Memory Technologies said its fifth-generation DRAM platform entered mass production, claiming at least 50% more gross dies per wafer and two 24-gigabit LPDDR5X products.
ChangXin Memory Technologies, China's leading DRAM producer, said on Sunday that its fifth-generation DRAM platform is already in mass production in Hefei. SemiAnalysis still maps that platform to a 1a-equivalent node, without the extreme-ultraviolet, or EUV, tools Samsung, SK hynix and Micron use, and in June projected CXMT would finish 2026 at about 350,000 DRAM wafer starts a month, just under roughly 385,000 for Micron.
Vice president Luo Xiaodong, who heads CXMT's marketing centre, said the company's process capability now matches the most advanced nodes the industry is mass-producing. Independent measurements of the new die were not published with the remarks.
The Hefei-based company, listed in Shanghai as 688825, said it had cut the spacing of key data-storage features to 11.95 nanometres by using quadruple patterning, a method that repeats lithography steps to draw finer lines. It said the platform can produce at least 50% more gross chip dies per wafer than its fourth-generation process, using an 8-gigabit chip as the baseline. Gross dies are the chips that can be drawn on a wafer, not the share that pass final testing.
CXMT also unveiled two 24-gigabit LPDDR5X products on the new platform, a low-power DRAM used mainly in smartphones, and said both were already in mass production. Each holds 50% more data than the company's previous equivalent parts and comes in two package formats. It named no handset or server customer, no qualification, and no final-test yield for the new chips.
How G5 compares with Samsung, SK hynix and Micron
Samsung in April 2024 said its LPDDR5X reached 10.7 Gbps on 12-nanometre-class technology, with packages up to 32GB, and had been verified with mobile processors. Micron in June 2025 said it was shipping qualification samples of 1-gamma LPDDR5X at the same 10.7 Gbps speed, using EUV, with capacities from 8GB to 32GB aimed at 2026 flagship phones. SK hynix said in March it had developed LPDDR6 on its 1c, sixth-generation 10-nanometre-class process.
A 24-gigabit die stores 3 gigabytes. CXMT's October 2025 LPDDR5X lineup already offered 12-gigabit and 16-gigabit dies in packages as large as 24GB, with 10,667 Mbps parts then only at customer sampling. Sunday's products are a denser die on a tighter process, which is how more chips fit on each wafer.
TechInsights in January 2025 measured CXMT's earlier G4 16-gigabit DDR5 die at a 16.0-nanometre feature size, a D1z-class part, while Samsung, SK hynix and Micron were already producing D1a and D1b chips in the 12-to-14-nanometre range. Sunday's 11.95-nanometre figure is CXMT's own spacing number for G5. Dylan Patel, Ray Wang and Myron Xie of SemiAnalysis wrote in June that they still suspected G4 yields sat below the 85% to 90% mature level they use for a 1z line, reading that from CXMT's 2024 and 2025 margins, and that G5 would face rising fabrication and design difficulty even without EUV.
CXMT's 10% DRAM share and the EUV limit
Counterpoint Research put CXMT at 10% of global DRAM revenue in the second quarter, behind Samsung at 38%, SK hynix at 25% and Micron at 24%. On Thursday, September 17, the South China Morning Post reported that ZTE-backed Nubia's NaviX Ultra used CXMT LPDDR5X, which the company called its first large-scale use of domestically made chips at that speed. That report did not say the phone used the two new 24-gigabit parts.
SemiAnalysis's June model, the same one that had CXMT just under Micron on 2026 wafer starts, had the company at 12% of DRAM bit shipments in 2027, from 9% in 2025. Those wafer and bit figures are forecasts of wafers in, not proven good bits out.
The shrink CXMT is now putting into volume is the one it can do with the tools it can buy. U.S. export controls since 2022 have restricted China's access to certain advanced chipmaking equipment and related software. Quadruple patterning is how a DRAM line draws tighter features when it does not have EUV. Micron's 1-gamma mobile parts used EUV. Nothing in Sunday's remarks quantified how far the controls slow a G5 ramp, or what share of wafers will actually run the new node.
The corporate backdrop is state-backed and newly public. CXMT listed on Shanghai's STAR Market on July 27 after raising $8.6 billion. It opened at 49.50 yuan against an 8.66 yuan offer price. Reuters in July put Hefei government-linked investors at 36.8%, and at roughly half of the company once Anhui provincial entities are included.
S&P Global Ratings said in August that DRAM and NAND prices had jumped about four to five times over the first half of 2026. Micron, the U.S. pure-play, is up 536% over 12 months through Friday and still 19% below its 52-week high of $1,255. TrendForce in early August projected third-quarter mobile DRAM contract prices would rise about 8% to 13% from the second quarter, a slower pace than the first-half spike, and did not tie that outlook to CXMT. No source has tied Sunday's production claim to a DRAM-price forecast.
The funds that hold Micron, and the two that hold CXMT
Most U.S. fund holders meet this story through Micron, not through Shanghai. The VanEck Semiconductor ETF SMH, which tracks U.S.-listed chipmakers and carries an A on etf.net's published scale, held Micron at 5.5% as of Friday, its fifth position in a $74.1 billion book led by Nvidia. The iShares Semiconductor ETF SOXX, also an A, held Micron at 8.8%, its third position, in a $45.4 billion fund. Neither discloses CXMT.
Micron is SOXX's third-largest holding, at 8.8%
- 9.3%
- 9.1%
- 8.8%
- 7.0%
- 5.8%
- 5.1%
- 4.8%
- 4.2%
- 4.0%
- 4.0%
CXMT's A-share is still off Stock Connect, so most foreign investors cannot buy it directly. A U.S. fund that wants the line uses a total-return swap. Two dedicated memory funds have done that. The Roundhill Memory ETF DRAM, an actively managed memory portfolio with a C, held a 5.1% CXMT swap. Tema's smaller memory ETF DISK, which does not yet have a published etf.net letter, is an $88.6 million fund with a 7.9% CXMT swap. Tema added CXMT on the morning of the July IPO, when the weight was 10.56%.
A holder of Micron or a semiconductor fund owns the same book they owned on Friday. Sunday's extra dies on the wafer become real when they clear a yield and show up in phones that used to buy Samsung and SK hynix.
Frequently asked
What did CXMT actually claim?
That its fifth-generation DRAM platform is in mass production in Hefei, packing at least 50% more gross dies per wafer than its fourth generation, along with two 24-gigabit LPDDR5X parts.
Does that put CXMT level with Samsung, SK hynix and Micron?
Not on the evidence published: the 11.95-nanometre figure is CXMT's own, no independent measurement or final-test yield accompanied it, and rivals are already shipping EUV-built LPDDR5X and developing LPDDR6.
Why does CXMT use quadruple patterning?
U.S. export controls since 2022 have restricted China's access to certain advanced chipmaking equipment, and quadruple patterning is how a DRAM line draws tighter features without EUV.
Can U.S. fund investors own CXMT?
Not directly, since the A-share is off Stock Connect; two dedicated memory ETFs hold it through total-return swaps, while mainstream semiconductor funds reach the story through Micron instead.